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Field of the Invention The present invention generally relates to memory systems and, more particularly, to methods for improving the performance of a dynamic random access memory and thereby improving the performance of an integrated circuit that includes the dynamic random access memory. 2. Description of the Related Art Dynamic random access memory (DRAM) is the dominant type of semiconductor memory used for main memory in computers and other devices. DRAMs provide rapid access to data through a memory cell comprising a capacitor and an access transistor, often referred to as a cell or storage node. The capacitor holds a charge that represents the data stored in the cell. The charge is accessed by read and write operations in which the access transistor controls the amount of charge on the capacitor. Advances in memory density and performance have greatly enhanced the capabilities of computing devices, particularly personal computers (PCs). One limitation of DRAM memories, however, has been their inability to access memory with the high speed needed for some applications. DRAM memories and DRAM memory controller performance are becoming more limiting as the speed of modem processors increases. Certain computer systems employing DRAMs have employed processor bypass modes to reduce memory access latency in such systems. For example, DRAMs typically have four banks of memory (DRAM memory) arranged in a matrix of rows and columns. Processors can access the row and columns of the memory array using a rank, which is a single row of memory within a bank of memory. To access memory more quickly, however, a PC can transfer or jump to a rank that is not currently executing, such as a rank that is referred to as “the next processor rank”. This operation, referred to as a “bank-interleave” of a rank, effectively eliminates all of the latency caused by the processor's access to the DRAM. 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